1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to memory address translation mechanisms for translating a virtual memory address to a physical memory address within data processing systems.
2. Description of the Prior Art
It is known to provide data processing systems with memory address translation circuitry, such as memory management units, which serve to translate a virtual address generated by a processor into a physical address for accessing a memory system. One way of performing the required translation is to use translation tables. These translation tables may be arranged as a hierarchy of translation tables with each level of the hierarchy taking one portion of the virtual address to index into a table to find either a pointer to a further level of table, or a descriptor which provides the target physical address. A top down page table walk operation is performed in which a sequence of indexed lookups into the different levels of the page tables are performed until the full virtual address has been translated into the target physical address. The significance of “top-down” is that the first level of table takes the most significant portion of the virtual address to index the table.
In many systems it is common that the address space is divided into 4 kB pages and address translation is performed with the granularity of this page size. Furthermore, the page tables (translation tables) are also arranged to have a size of 4 kB so that they efficiently fit within pages of memory allocated to store those page tables.
Considerable amounts of software exists which either explicitly or implicitly rely upon the memory address space being divided into 4 kB pages. Such software may not operate correctly if the page size is varied.